1. Field of the Invention
The present invention relates to a method for operating a semiconductor memory device having a plurality of operating modes and a semiconductor memory device having a plurality of operating modes.
2. Description of the Related Art
Conventionally, semiconductor memory devices such as DRAMs receive a different address signal from the same address terminal at twice in order to reduce the number of terminals. Such a semiconductor memory device receiving multiplexed address signals can be molded in a small package in spite of its large memory capacity.
A synchronous DRAM (SDRAM) is known as another semiconductor memory device to receive multiplexed address signals. The SDRAM is a memory device that operates input/output interfacing circuits at high speed in synchronization with a clock signal and write and read data at high speed.
The SDRAM is capable of performing read and write operations in a plurality of memory cells connected with a same word line, at high speed. However, in memory cells connected with different word lines, the word lines must be selected at a timing similar to that in the prior art DRAMs. Therefore, an access time in a random access is equivalent to that in the DRAMs.
An operating mode of SDRAMs is determined upon inputting a command once; then, the SDRAMs perform the operating mode determined. Due to this, a number of terminals for receiving multiple command signals such as a chip select signal (/CS), row address strobe signal (/RAS), column address strobe signal (/CAS), write enable signal (/WE), and clock enable signal (CKE) are required. In addition, as the sequence of inputting commands is not predetermined, a timing of performing a precharge operation of a bit line can not be generated inside of a chip. Accordingly, precharging a bit line needs to be performed by supplying a command from the exterior of the chip.
In recent years, fast cycle RAM (FCRAM) have been developed as DRAMs whose operation cycle is significantly shortened to perform data read/write operation at high speed during random accessing.
The FCRAM is designed so that its internal operation is divided into three stages. An operation in each stage is completed automatically. This makes it possible to perform a pipeline processing not only for data input/output units but also for an address accepting an operation and an operation of a memory core unit. The use of such pipeline processing makes it possible to shorten the operating cycle. Additionally, as the FCRAM is designed to achieve shortening an access time as a top priority, address terminals are non-multiplexed and all address signals are supplied at the same time of inputting a command. Upon inputting a single command, an operating mode is determined and then the predetermined operating mode is performed.
The above-described SDRAMs have a disadvantage that these require a great number of command input terminals. An increase in number of command input terminals complicates a configuration of circuit, which controls a command input, on printed wiring boards.
The above-noted FCRAMs have a disadvantage that, when compared to DRAMs and SDRAMs having equal memory capacities, they require more terminals because of non-multiplexed addressing. An increase in terminal number results in increases in associative components such as address pads and address input circuits and others, which causes a problem that the chip size gets larger. Another disadvantage is that such increase in terminal number can cause the package size to likewise increase. In particular, in the case CSP (chip size package) which has been becoming a mainstream in the art, balls connected to a printed wiring board are laid out in the form of two-dimensional arrangement thereon. This may result in an increase in size of package depending upon the number of terminals.
An object of the present invention is to reduce the number of terminals necessary for inputting commands and addresses.
Another object of the present invention is to prevent an increase in chip size and its package size by reducing the number of terminals.
Still another object of the present invention is to retain an operation cycle at high speed even when terminals decrease in number.
Further object of the invention is to especially accept a signal at high speed in order to retain an operation cycle at high speed.
According to one of the aspects of the method for operating a semiconductor memory device in the present invention, signals supplied to predetermined terminals are accepted as commands at a plurality of times, the number of operating modes is sequentially narrowed down based on the command each time and an internal circuit is controlled according to the narrowed operating modes. Since the information necessary for determining an operating mode is accepted at a plurality of times, the number of terminals necessary for inputting commands can be reduced. In particular, in case of inputting commands at a dedicated terminal, its input pads, input circuits, or the like are no longer be required so that the chip size can be reduced. One example is that four or eight operating modes may be identified respectively when commands are accepted at two or three times at two terminals. The reduction is accomplished by reducing the number of terminals, which gives limits to the package size.
According to another aspect of the method for operating, a semiconductor memory device in the present invention, commands are accepted at twice. The number of operating modes are narrowed down by the first command. At this time, a part of the circuit necessary for performing a predetermined operating mode among the narrowed operating modes is operated. Then, an operating mode is determined by the second command; when the operating mode is a predetermined operating mode, the remainder of the circuit is operated. Performing a part of the predetermined operating mode in advance makes it possible to shorten the access time even in the case of accepting commands at twice.
According to still another aspect of the method for controlling a semiconductor memory device in the present invention, a mode register setting mode without accompanying any internal operation is such that the operation can be completed within a predetermined period even when an operation is initiated after the receipt of the second command. Similarly, a data retaining mode does not require inputting /outputting data from/to the exterior so that the operation may be completed within a predetermined period even when the operation is initiated after the receipt of the second command.
According to yet another aspect of the method for controlling a semiconductor memory device in the present invention, it is unnecessary to accept information for setting the mode register together with the first command from an address terminal. Therefore, it is unnecessary to retain the information until the second command is supplied; as a result, it is possible to prevent the complication of a controlling circuit.
According to further aspect of the method for operating a semiconductor memory device in the present invention, the control necessary for shifting to the data retaining mode is performed when an operating mode determined by the second command is a data retaining mode. Thereafter, the control necessary for shifting to a standby mode is performed when a signal supplied to a predetermined terminal is set at a predetermined level during the data retaining mode. By monitoring a signal at a predetermined terminal other than by a command, it is possible to shift to another operating mode during a predetermined operating mode.
According to further aspect of the method for operating a semiconductor memory device in the present invention, the control necessary for shifting to a self refresh mode is performed when a signal supplied to a predetermined terminal is set at a predetermined level during an auto refresh mode. A difference between the auto refresh and self refresh modes is that the former is given a refresh timing from the exterior whereas the latter generates such timing by, itself. An identical circuit is used for performing both a refresh counter operation and a refresh operation. Therefore, the auto refresh mode continuously and smoothly shifts to the self refresh mode, shortening the time required for the shifting.
According to further aspect of the method for operating a semiconductor memory device in the present invention, the acceptance of the first command is inhibited by a signal supplied to a predetermined terminal and the device becomes a standby state. When a signal supplied to another predetermined terminal reaches a predetermined level in the standby state, the control for shifting to the standby mode is performed. By monitoring a signal at a predetermined terminal while inhibiting the input of the first command, it is possible to shift to another operating mode other than by a command.
According to another aspect of the method for operating a semiconductor memory device in the present invention, when a signal supplied to a predetermined terminal reaches a predetermined level while the device is in the standby state, the control for shifting to a low power consumption mode is performed. In this low power consumption mode, the device is in a static state and is not directly related to an access operation. The control for shifting to the low power consumption mode is performed by supplying a predetermined signal to a terminal, which results in the improved usability.
According to further aspect of the method for operating a semiconductor memory device in the present invention, the first and second commands are accepted in synchronization with a clock signal. The second command is accepted a half or one clock after the acceptance of the first command. Accordingly, the information of the second command is obtainable in a short time after the acceptance of the first command. As a result, any delay in controlling the second command may be minimized when accepting commands at twice.
According to another aspect of the method for operating a semiconductor memory device in the present invention, a write operation mode and a read operation mode are distinguished by the first command. In other words, the operating modes narrowed down by the first command does not include both the write and read operation modes. After the acceptance of the first command, the circuit common to both the write and the read operation modes initiates the operation. Starting the operation of such circuit necessary for the write and read operation modes in advance makes it possible to shorten the access time.
According to still another aspect of the method for operating a semiconductor memory device in the present invention, a signal supplied to an address terminal by the first command is accepted as a part of an address necessary for a write or a read operation. When an operating mode determined by the second command is either the write or the read operation mode, a signal supplied to the address terminal is accepted as the remainder of the address required for the write or the read operation. Accepting the address necessary for the write or the read operation at twice results in significantly reducing the number, of address terminals. Consequently, the number of address pads, address input circuits or the like are decreased and the chip size can be reduced. The reduction is accomplished by reducing the number of terminals, which gives limits to the package size.
According to still another aspect of the method for operating a semiconductor memory device in the present invention, a word line is selected prior to the receipt of the second command to shorten the access time.
According to further aspect of the method for operating a semiconductor memory device in the present invention, when an operating mode determined by the second command is an auto refresh mode, a word line corresponding to the address accepted together with the first command, is unselected. Then, a word line corresponding to a refresh address internally generated, is selected. Memory cells are reliably refreshed by switching over the selection of a word line.
According to yet another aspect of the method for operating a semiconductor memory device in the present invention, at least a sub-word line is specified and selected according to an address accepted together with the first command. After the acceptance of the first command, it is possible to control the circuit required for operating predetermined memory cells prior to the receipt of the second command. Accordingly, the access time may be shortened.
According to yet another aspect of the method for operating a semiconductor memory device in the present invention, the activation of a column decoder is first initiated by the first command. When the operating mode determined by the second command is either a write operation mode or a read operation mode, an address accepted is used to select a column selecting line. The access time may be shortened since the column decoder is activated in advance before determining the address to select the column selecting line.
According to further aspect of the method for operating a semiconductor memory device in the present invention, a signal supplied to a predetermined terminal is accepted as information for specifying the length of write data when the operating mode determined by the second command is the write operation mode. The length of write data is directly controlled based on the information accepted. Accordingly, in case a plurality of data is accepted in succession from an input/output terminal(s) during the write operation, it is possible to change the length of data accepted under the simple control procedures. In addition, with regard to data unnecessary to be written (that is, a portion longer than the length of data specified), any write control is not required. This saves a time taken to control the write operation. Thus, it is possible to make an input timing of the first command earlier in the next cycle. The length of write data can be changed only by the control of the input/output circuits so that the control may be reliably performed by accepting information together with the second command.
According to further aspect of the method for operating a semiconductor memory device in the present invention, a signal supplied to a predetermined terminal is accepted as masking information which invalidates a part of write data supplied in succession when the operating mode determined by the second command is the write operation mode. A part of the write data is masked based on the masking information accepted. To control the masking information by a dedicated terminal, the information has to be accepted from the dedicated terminal at each time of performing the write operation and that makes the control procedure complicated. Accepting the masking information together with the second command makes it possible to easily control the masking of write data.
According to further aspect of the method for operating a semiconductor memory device in the present invention, a signal supplied to a predetermined terminal is accepted as information for specifying the length of read data when the operating mode determined by the second command is the read operation mode. The length of read data is directly controlled based on the information accepted. Accordingly, in case a plurality of data is accepted in succession from an input/output terminal(s) during the read operation, it is possible to change the length of data accepted under the simple control procedure. In addition, with regard to data unnecessary to read (that is, a portion longer than the length of data specified), any output control is not required. This saves a time taken to control the read operation. Thus, it is possible to make an input timing of the first command earlier in the next cycle. The length of read data can be changed only by the control of the input/output circuits so that the control may be reliably performed by accepting information along with the second command.
According to further aspect of the method for operating a semiconductor memory device in the present invention, a signal supplied to a predetermined terminal is accepted as masking information which invalidates a part of read data supplied in succession when the operating mode determined by the second command is the read operation mode. A part of the read data is masked based on the masking information accepted. To control the masking information by a dedicated terminal, the information has to be accepted from the dedicated terminal at each time of performing the write operation and this makes the control procedure complicated. Accepting the masking information together with the second command makes it possible to easily control the masking of write data.
According to a further aspect of the method for operating a semiconductor memory device in the present invention, in case that the operating modes corresponding to the first command include the write operation mode, the write data and the addresses accepted in the previous write operation mode are used to perform the write operation. This makes it possible to complete the write cycle early. In the case of performing a read operation after a write operation, it is possible to initiate the read operation early.
According to another aspect of the method for operating a semiconductor memory device in the present invention, in case that the operation modes narrowed down, upon the inputting of the first command, include a write operation mode, a part of the circuit necessary for performing a write operation is operated. When the operation mode determined by the inputting of the second command is an auto refresh mode, a refresh operation is carried out after the performance of the write operation. Thus, it is possible to effectively perform the write operation by utilizing the circuit which has initiated its operation by the inputting of the first command.
According to another aspect of the semiconductor memory device in the present invention, a command controlling circuit is comprised. The command controlling circuit accepts signals supplied to predetermined terminals as commands at a plurality of times, sequentially narrows down the number of operating modes based on the command each time and controls an internal circuit according to the narrowed operating mode. Since the information necessary for determining operating mode is accepted at a plurality of times, the number of terminals necessary for inputting commands can be reduced. In particular, in case of inputting commands at a dedicated terminal, its input pads, input circuits, or the like are no longer be necessary so that the chip size can be reduced. The reduction is accomplished by reducing the number of terminals, which gives limits to the package size. One example is that four or eight operating modes may be respectively identified when commands are accepted at two or three times at two terminals.
According to another aspect of the semiconductor memory device in the present invention, the command controlling circuit accepts commands at twice, narrows down a plurality of operating modes by the first command, and operates a part of the circuit necessary for performing a predetermined operating mode among the narrowed modes. The command controlling circuit determines an operating mode by the second command. When the operating mode is a predetermined operating mode, the remainder of the circuit is operated.
The number of terminals necessary for accepting commands can be reduced since the information necessary for determining an operating mode is accepted at a plurality of times. In particular, in case of inputting commands at a dedicated terminal, its input pads, input circuits, or the like are no longer be necessary so that the chip size can be reduced. The reduction is accomplished by reducing the number of terminals, which gives limits to the package size. Performing a part of the predetermined operating mode in advance makes it possible to shorten the access time even in the case of accepting commands at twice.
According to further aspect of the semiconductor memory device in the present invention, the command controlling circuit comprises a plurality of accepting circuits. Each of the accepting circuits respectively accepts signals, supplied at a plurality of times, each time. In other words, in accordance with the timing of the signal supplement, a different accepting circuit is respectively operated and the internal circuit is controlled. Accordingly, a command controlling circuit may be readily designed even in the semiconductor memory device which has a complicated command combination. Consequently, it is able to facilitate the verification of the design.
According to another aspect of the semiconductor memory device in the present invention, each of accepting circuits accepts signals in synchronization with the different edges of a clock signal. Due to directly accepting the signals by the same clock signal, the accepting procedure speeds up. This makes it possible to initiate an operation of the internal circuit early and shorten the access time.
According to still another aspect of the semiconductor memory device in the present invention, a timing generator, which generates a plurality of accepting signals based on a clock signal, is comprised. Each of accepting circuits respectively accepts signals in synchronization with the accepting signals. It is no longer necessary to wire the clock signal to the plurality of accepting circuits because the signals are accepted utilizing the accepting signals generated from the clock signal. As a result, even when signals supplied and the accepting circuits are substantial in number, the signals can be accepted without increasing the load of the clock signal.